Flash memory is a type of semiconductor computer memory with many desirable characteristics. Like read only memory, ROM, it is non-volatile, meaning that the contents of the memory are stable and retained without applied electrical power.
Flash memory devices have found wide commercial success in the electronic device market. A major advantage of flash over ROM is that the memory contents of flash may be changed after the device is manufactured. Flash memory has found wide acceptance in many types of computers, including desktop computers, mobile phones and hand held computers. Flash memory is also widely used in digital cameras and portable digital music players, for example “MP3” players.
In addition to direct flash storage applications, for example in video cameras, flash-based storage devices are replacing rotating magnetic disks, sometimes known as hard drives, in many applications. Compared to hard drives, flash is significantly more rugged, quieter, lower power, and for some densities such a flash based device may be smaller than a comparable hard drive.
A flash memory typically comprises an array of cells that can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual-Metal-Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET, or flash memory cell includes a source, drain, floating gate or nitride storage layer and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. Programming occurs by hot electron injection in order to add charge to the floating gate or nitride layer. Erasure employs Fowler-Nordneim tunneling effects in which electrons punch through a thin dielectric layer, thereby reducing the amount of charge on the floating gate or nitride layer. Erasing a cell typically sets the logical value of the cell to “1,” while programming a cell sets the logical value to “0.” The flash memory cell provides for nonvolatile data storage.
FIG. 1 shows a memory cell 10 as has been well known in the conventional art. Region 14 is the source region for memory cell 10, and is typically created by implantation of dopant materials, for example N-type (or n+) dopants. Region 15 is the drain of cell 10, and is created by similar processes to source 14. In many memory cells, regions 14 and 15 are constructed substantially similarly, and either region may be used as source and/or drain interchangeably. Control gate 16 is used to control the operation of memory cell 10. A p-well region 17 is formed between source/drain regions 14. Feature size 18 is the nominal size of the smallest feature that can be created by a particular semiconductor process. In memory cells of this type, the gate 16 width and channel 17 length typically correspond approximately to feature size 18.
Memory cell 10 may be one of two general types of non-volatile memory, a “floating gate” cell or a nitride read only memory (NROM) cell. In a floating gate cell, layer 12B of the gate stack is typically conductive polysilicon. Layers 12A and 12C are insulating materials which isolate or “float” gate layer 12B, which is usually referred to as a floating gate. Floating gate 12B is the storage element of memory cell 10.
Silicon nitride based flash memory has many advantages as compared to its floating gate and tunneling oxide based counterparts. Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) is potentially very dense in terms of number of cells per unit area that can be used and it requires fewer process steps as compared to floating gate memory. Moreover, it can be easily integrated with standard SRAM process technology. A further advantage of using SONOS devices is their suitability for applications requiring large temperature variations and radiation hardening. The SONOS stack is a gate dielectric stack and consists of a single layer of polysilicon, a triple stack ONO (Oxide-Nitride-Oxide) gate dielectric layer and a MOS channel 17. The ONO structure may consist of a tunnel oxide 12A, a nitride memory storage layer 12B and a blocking oxide layer 12C.
To read a bit stored in memory cell 10, the control gate 16 is brought to a read voltage of about 4 volts and the source 14 is grounded. Any charge present on storage layer 12B influences the amount of current flowing through the device, e.g., from source 14 to drain 15. Sensing logic connected to a bit line comprising the cell compares the magnitude of the current flowing in memory cell 10 to the current of a read reference cell in order to determine if a bit is stored in memory cell 10. E.g., if a current flowing in reference cell 10 is greater than a current of a read reference cell, memory cell 10 is said to be programmed, and the cell is read as a binary “0.”
To write (or program) a bit into memory cell 10, control gate 16 is brought to a programming voltage of about 9 volts, the drain 14 is brought to a voltage of about 5.0 volts, and source 15 is grounded. The resulting current flow causes hot carrier injection of charge into storage layer 12B. A programming operation is typically followed by a “program verify” operation which performs a read of the programmed bits to ensure that they were completely and properly programmed.
To erase memory cell 10, a voltage of about −9 volts is applied to control gate 16. P-well region 17 has about +9 volts applied. In response to the applied voltage, charge migrates off of storage layer 12B via Fowler-Nordheim tunneling. These voltages are typically applied in the form of a pulse, or series of pulses, known as an erase pulse. A typical erase pulse may be approximately within the range of 0.1 ms to 10 ms in duration.
Following an erase pulse, an “erase verify” operation is performed. An erase verify operation is similar to a read verify operation in that each cell in an “erased” sector is read to verify that the cell is completely and thoroughly erased. For an erase verify operation, rather than a read reference cell, a special erase reference cell, which is typically at a slightly lower voltage than a read reference cell, is used in a current comparison operation.
If an erase verify operation determines that one or more cells are not erased, then another erase pulse is generated. A sequence of erase pulses followed by erase verify operations typically continues until all cells verify as erased. A typical erase time for a sector of flash memory cells is about 100 ms.
FIG. 2 illustrates a typical configuration of a plan view of a section of a memory array 100 in a NOR-typc of configuration for a memory device. FIG. 2 is not drawn to scale. As shown in FIG. 2, the array 100 is comprised of rows 110 and columns 120 of memory cells. Each of the memory cells is isolated from other memory cells by insulating layers (e.g., a plurality of shallow trench isolation regions (STI) 150).
The control gates of each of the memory cells are coupled together in each of the plurality of rows 110 of memory cells, and form a plurality of word lines 130 that extend along the row direction.
Bit lines extend in the column direction and are coupled to drain regions via drain contacts 168 in an associated column of memory cells 120. The bit lines are coupled to drain regions of memory cells in associated columns of memory cells 120.
A plurality of source lines 140 extend in the row direction and are coupled to the source regions of each of the memory cells in the array of memory cells 100. One source line is coupled to source regions in adjoining rows of memory cells, and as a result, one source region is shared between two memory cells. Similarly, drain regions are shared amongst adjoining rows of memory cells, and as a result, one drain region is shared between two memory cells.
A plurality of source contacts are coupled to the plurality of common source lines 140. Each of the plurality of source contacts 145 is formed in line with the associated common source line to which it is coupled. The source contacts are formed in a column 160, and may be coupled with each other. The column 160 is isolated between two STI regions and forms a dead zone in which no memory cells are present.
It is to be appreciated that due to the NOR architecture of array 100, numerous drains are coupled together to form a bit line. For example, 512 cells may be attached to a common bit line. Unfortunately, if a single cell becomes leaky, e.g., it has been “over erased” and the cell has entered a depletion mode of operation, that cell will conduct high levels of current, even when that cell is not being directly accessed. A single such over erased cell may cause all cells coupled to the same common bit line as the over erased cell to appear to be erased. For example, during a read or erase verify operation, a cell that has not been erased may falsely appear to actually be erased as a result of current flowing on a common bit line from an over erased cell.
A conventional approach to mitigate false erase verifies due to over erased cells is to recover over erased cells. For example, after every erase pulse, and prior to an erase verify operation, a search is performed to detect leaky columns, which may contain over erased cells. For example, a modified read operation with approximately 0 volts applied to the word line may be performed. If a bit line is determined to contain a leaky cell, a recovery operation is performed.
A recovery operation may comprise applying approximately +5 volts to the drain of the bit line, approximately 0 volts on the source of the drain line and approximately 0 volts on the gate. The application of these voltages is designed to “soft” or partially program a leaky cell. Each column containing an over erased cell may take from about 100 μs to 1 ms of such applied voltages to correct the over erasure.
Flash memory generally must be erased, either in its entirety or in large segments called pages, prior to changing its contents. Erasing a flash device, or a portion of a flash device, is generally a long process, typically measured in hundreds of milliseconds. This is a disadvantage compared to RAM and hard drives, which may be written directly, without an interposing erasure. Unfortunately, having to insert additional steps, for example, searching for and recovering over erased cells, into the basic erase cycle detrimentally increases the time required to erase flash memory.
Semiconductor processing equipment is extremely expensive. Fundamental semiconductor processing steps, e.g., implantation and diffusion, typically require long periods of development and extensive qualification testing. Implementing a new fabrication process requires considerable resources on the part of the semiconductor manufacturer. A manufacturer may have to alter or entirely revamp process libraries and process flows in order to implement a new fabrication process. Additionally, re-tooling a fabrication line is very expensive, both in terms of direct expenses as well as in terms of opportunity cost due to the time required to perform the re-tooling. Consequently, any solution to increase the rate of flash programming should be compatible with existing semiconductor processes and equipment without the need for revamping well established tools and techniques.
Accordingly, a need exists to increase the erase speed of flash memory. A further need exists for increasing the erase speed of flash memory in a manner that is compatible and complimentary with conventional approaches to increase the programming speed of flash memory. A still further need exists for the above mentioned needs to be achieved with existing semiconductor processes and equipment without revamping well established tools and techniques.